1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device that has an air bridge structure, and a method for manufacturing such as semiconductor device.
2. Description of the Related Art
In semiconductor devices, it is important to reduce the as parasitic capacitances between wires. Capacitance between neighboring wires or between upper and lower wires is a cause of a reduction in circuit speed.
In order to reduce parasitic capacitance, the usual method used is that of employing an insulating material having a low dielectric constant as an interlayer insulation film. However, the dielectric constant of an inorganic material that can withstand temperatures of approximately 400.degree. C. is no lower than approximately 3, and with organic materials although there are materials with a dielectric constant of approximately 2, these materials, not being heat resistant, are impractical. For this reason, an air bridge interconnect has been proposed, in which the interlayer insulation film is removed, leaving just the metal interconnect. In this construction, because there is air (having a dielectric constant of 1) between the metal interconnects, it is possible to reduce the parasitic capacitance to the very minimum value. However, if the interconnect becomes long in the floating condition, problems caused by deformation, such as interconnect peeling and shorts caused by interconnect sagging occur.
Because of the above-noted problems, there is disclosed in Japanese Patent No. 2705556 the prevention of deformation of interconnects, by providing supporting posts at a fixed interval beneath a floating metal interconnect.
The above-noted disclosure is described below, with reference made to drawings. FIG. 13 is a perspective view that shows in conceptual form the above-noted technology, this showing a semiconductor integrated circuit having a two-layer wiring structure. In this device, a silicon substrate 101 has a silicon nitride (Si.sub.3 N.sub.4) film 102 as a protective layer and etching stopper, a first aluminum interconnect 103 extending in a prescribed direction on top of first post-shaped interlayer insulation film 104, which are formed by postshaped CVD oxide film 105 that are formed at a uniform pitch, these first post-shaped interlayer insulation film 104 forming an air bridge structure that maintains a prescribed distance with respect to the silicon nitride film 102. In this case, a silicon nitride film 106 is also formed below the first aluminum interconnects 103, as an etching stopper.
The second aluminum interconnects 107, which are formed on top of the first aluminum interconnects 103 extend in a direction that is perpendicular to the first aluminum interconnects 103 and, similar to the first aluminum interconnects 103, these second aluminum interconnects 107 are maintained at a prescribed distance with respect to the silicon nitride film 102 by second post-shaped interlayer insulation films 108, which have a film thickness that is greater than that of the first post-shaped interlayer insulation films 104 and which are formed at a uniform interval. In this case, the second post-shaped interlayer insulation films 108 are formed as laminates of the above-noted post-shaped CVD oxide film 105, a silicon nitride film 106, and a post-shaped CVD oxide film 109. In this case as well, a silicon nitride film 110 is provided under the second aluminum interconnects 107, as an etching stopper.
Therefore, according to the above-noted construction, the first aluminum interconnects 103 and second aluminum interconnects 107 make contact with no elements other than the post-shaped interlayer insulation films 104 and 108, the surrounding area being a void, so that there is no insulation film between the first aluminum interconnects 103 and the second aluminum interconnects 107, thereby greatly reducing the wiring capacitance therebetween.
The method of manufacturing the above-noted wiring structure is described below. First, as shown in FIG. 14(a), a silicon nitride film 102 and a CVD oxide film 105' are formed on a silicon substrate 101. Then, as shown in FIG. 14(b), photolithography technology and oxide film etching technology are used to pattern the CVD oxide film 105' over the entire chip in a matrix pattern that is skewed by half pitch with the first aluminum interconnects 103 that are to be formed later, thereby forming a matrix CVD oxide film 105". Then, a silica film 111 is formed over the entire wafer, the resulting plan-view structure being shown in FIG. 14(c). FIG. 14(b) is a cross-section view along the line A--A that is shown in FIG. 14(c). In order to form the matrix CVD oxide film 105" over the entire semiconductor device at a uniform pitch, the silica film 111 is formed uniformly flatly over the entire surface. In this case, it possible to use an applied film such as a polyimide organic film instead of the silica film.
Next, as shown in FIG. 15(a), the applied silica film 111 is baked to cure the film, the resulting flat applied silica film 111 being etched over its entire surface to expose the surface of the matrix CVD oxide film 105", after which a silicon nitride film 106 and a first aluminum interconnect layer 103 are formed over the entire surface. At this point, although not shown in the drawing, in the case in which a contact is formed for the purpose of connection between the silicon substrate 101 and the first aluminum interconnects 103, after growing the silicon nitride film 106, before forming the first aluminum interconnect layer 103', photolithography technology and etching technology are used to form a contact hole in the silicon nitride film 106 and matrix CVD oxide film 105" and applied silica film 111 and silicon nitride film 102. The contact is formed by the growth of the first aluminum interconnect layer 103' and the filling of a via hole by tungsten or the like.
Then, as shown in FIG. 15(b), the first aluminum interconnect layer 103' is patterned using photolithography and aluminum etching technologies, thereby forming the first aluminum interconnects 103. FIG. 15(c) is the construction shown in plan view, and FIG. 15(b) is a cross-section view along the line B--B that is shown therein. It can be seen from the above that the first aluminum interconnects 103 are arranged in a vertical direction as shown in the drawings, and extend over the entire surface of the semiconductor device at a uniform pitch, and there is a half-pitch skew with respect to the matrix CVD oxide film 105".
Next, as shown by the broken lines in FIG. 16(a), a CVD oxide film 109' is grown on the exposed surface of the first aluminum interconnects 103 and silicon nitride film 106, this having a thickness that is greater than that of the first aluminum interconnects 103. Then, using the mask that was used to form the matrix CVD oxide film 105", photolithography and etching technologies are used to form the second matrix CVD oxide film 109", which is on-line overlapped with the matrix CVD oxide film 105". Additionally, the silicon nitride film 106 other than the lower part of the first aluminum interconnects 103 and the second matrix CVD oxide film 109" is etched, after which an applied silica film 112 is formed and the surface is flattened.
Next, as shown in FIG. 16(b), the entire surface of the applied silica film 112 is etched from above, so as to flatten the second matrix CVD oxide film 109". Over this entire surface, a silicon nitride film 110 is formed. FIG. 16(c) is a plan view of the above-noted condition, and FIG. 16(b) is a cross-section view along the direction of line C--C thereof. In the case in which via hole is to be formed for the purpose of connecting the first aluminum interconnects 103 and the second aluminum interconnects 107, similar to the case of the contact formation, a hole is formed in the applied silica film 112 and the silicon nitride film 110.
Next, as shown in FIG. 17(a), a second aluminum interconnect layer 107' is grown over the entire surface and photolithography and aluminum etching technologies are used to performing patterning of the second aluminum interconnects 107 and applied silica film 110 in a direction that is perpendicular to the wiring direction of the first aluminum interconnects 103, at the same pitch as the first aluminum interconnects 103, and skewed a half pitch with respect to the above-noted second matrix CVD oxide film 109". The condition after performing this patterning is shown in plan view in FIG. 17(b).
Then, as shown in the cross-section views of FIGS. 18 (a), (b), and (c), along the directions of lines E--E, F--F, and G--G, respectively, anisotropic etching is done from the top of the second aluminum interconnects 107, the second matrix CVD oxide film 109" and the applied silica film 112 except below the second aluminum interconnects 107 being etched until the first aluminum interconnects 103 are exposed. Additionally, when etching proceeds further the first aluminum interconnects 103 are exposed, after which etching is done of the matrix CVD oxide film 105" and the applied silica film 110 until the silicon nitride film 102 on the silicon substrate 101 is exposed, using the second aluminum interconnects 107 and the matrix CVD oxide film 105" as a mask. By doing this, the second post-shaped interlayer insulation film 108 below the second aluminum interconnects 107, which is on-line aligned with the silicon nitride film 110, the second post-shaped matrix CVD oxide film 109, the silicon nitride film 106, and the post-shaped CVD oxide film 105 is formed with a uniform pitch on the silicon nitride film 102 on the silicon substrate 101.
In a region in which this second post-shaped interlayer insulation film 108 does not exist, there exists the applied silica films 112 and 111 and a first aluminum interconnects 103, which is surrounded by the applied silica films 112 and 111. In a region in which only the first aluminum interconnect 103 exists, a post-shaped CVD oxide film 105 is formed with a uniform pitch on a silicon nitride film 102 on the silicon substrate 101, along with an applied silica film 111 that is surrounded by this post. Additionally, by performing wet etching using fluorine or the like for a short period of time only the applied silica films 111 and 112, which have a very fast etching rate compared to a CVD oxide film, are etched.
As a result, the applied silica films 111 and 112 parts become the hollows 113, thereby forming a first aluminum interconnect 103 having an air bridge structure that is supported by the first post-shaped insulation film 104, and a second aluminum interconnect 107 having an air bridge structure that is supported by the second post-shaped insulation film 108.
Therefore, the first aluminum interconnect 103 and the second aluminum interconnect 107 are supported independently by the post-shaped insulation films 104 and 108, which have different heights above the silicon nitride film 102 on the silicon substrate 101, and in an interconnect that has the minimum width, there is only a space between the first aluminum interconnect 103 and the second aluminum interconnect 107, enabling a great reduction in the wiring capacitance.
Because the above-noted technology enables the provision of insulating posts regardless of the positional relationship between upper wiring and lower wiring (the region in which wiring crosses or region in which wiring is isolated), it achieves a given effect with respect to wiring.
This method, however, in addition to the usual process steps for forming wiring, requires lithography and the like for formation of the insulation posts, this representing the problem of added process steps and an increased number of masks.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks of the prior art by particularly providing a novel semiconductor device in which air bridged wiring can be formed that has insulation posts, without an increase in the number of process steps or an increase in the number of masks, and a method of manufacturing the above-noted semiconductor device.